[RISCV] Add Smrnmi extension #111668

dong-miao · 2024-10-09T12:19:31Z

This commit has completed the Extension for Resumable Non Maskable Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:"Smrnmi" Extension

github-actions · 2024-10-09T12:19:59Z

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

llvmbot · 2024-10-09T16:48:15Z

@llvm/pr-subscribers-backend-risc-v

Author: None (dong-miao)

Changes

This commit has completed the Extension for Resumable Non Maskable Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:"Smrnmi" Extension

Full diff: https://github.com/llvm/llvm-project/pull/111668.diff

11 Files Affected:

(modified) clang/test/Preprocessor/riscv-target-features.c (+9)
(modified) llvm/docs/RISCVUsage.rst (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+9)
(modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+8)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+3)
(modified) llvm/test/MC/RISCV/machine-csr-names.s (+60)
(modified) llvm/test/MC/RISCV/priv-invalid.s (+2)
(modified) llvm/test/MC/RISCV/priv-valid.s (+4)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1)

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 05a8534ba13da1..9e986f0143aefa 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -30,6 +30,7 @@
 // CHECK-NOT: __riscv_smcdeleg {{.*$}}
 // CHECK-NOT: __riscv_smcsrind {{.*$}}
 // CHECK-NOT: __riscv_smepmp {{.*$}}
+// CHECK-NOT: __riscv_smrnmi {{.*$}}
 // CHECK-NOT: __riscv_smstateen {{.*$}}
 // CHECK-NOT: __riscv_ssaia {{.*$}}
 // CHECK-NOT: __riscv_ssccfg {{.*$}}
@@ -1449,6 +1450,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
 // CHECK-SMEPMP-EXT: __riscv_smepmp  1000000{{$}}
 
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32ismrnmi1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64ismrnmi1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
+// CHECK-SMRNMI-EXT: __riscv_smrnmi  1000000{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32izfa -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5736f3807f131b..a7ea36191283a3 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -129,6 +129,7 @@ on support follow.
      ``Smcdeleg``      Supported
      ``Smcsrind``      Supported
      ``Smepmp``        Supported
+     ``Smrnmi``        Supported
      ``Smstateen``     Assembly Support
      ``Ssaia``         Supported
      ``Ssccfg``        Supported
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3d0e1dae801d39..10b18e33f2abb2 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -931,6 +931,10 @@ def FeatureStdExtSmepmp
     : RISCVExtension<"smepmp", 1, 0,
                      "'Smepmp' (Enhanced Physical Memory Protection)">;
 
+def FeatureStdExtSmrnmi
+    : RISCVExtension<"smrnmi", 1, 0,
+                     "'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">;
+
 def FeatureStdExtSmcdeleg
     : RISCVExtension<"smcdeleg", 1, 0,
                      "'Smcdeleg' (Counter Delegation Machine Level)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5d329dceac6519..485fe386187c53 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
+def riscv_mnret_glue : SDNode<"RISCVISD::MNRET_GLUE", SDTNone,
+                             [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_selectcc  : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>;
 def riscv_brcc      : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC,
                              [SDNPHasChain]>;
@@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
   let rs1 = 0;
   let rs2 = 0b00010;
 }
+
+def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
+  let rd = 0;
+  let rs1 = 0;
+  let rs2 = 0b00010;
+}
 } // isBarrier = 1, isReturn = 1, isTerminator = 1
 
 def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
@@ -1581,6 +1589,7 @@ def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
 def : Pat<(riscv_sret_glue), (SRET)>;
 def : Pat<(riscv_mret_glue), (MRET)>;
+def : Pat<(riscv_mnret_glue), (MNRET)>;
 
 let isCall = 1, Defs = [X1] in {
 let Predicates = [NoStdExtZicfilp] in
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index d85b4a9cf77b33..faec8d0b5bc003 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -276,6 +276,14 @@ foreach i = 0...15 in {
 foreach i = 0...63 in
   def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
 
+//===----------------------------------------------------------------------===//
+// Machine Non-Maskable Interrupt Handling
+//===----------------------------------------------------------------------===//
+def:SysReg<"mnscratch",0x740>;
+def:SysReg<"mnepc",0x741>;
+def:SysReg<"mncause",0x742>;
+def:SysReg<"mnstatus",0x744>;
+
 //===----------------------------------------------------------------------===//
 // Machine Counter and Timers
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 86ce368bc1db66..aa27d63bfa6262 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -118,6 +118,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
+; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
@@ -261,6 +262,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
+; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
@@ -410,6 +412,7 @@
 ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
 ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
+; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
 ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
@@ -551,6 +554,7 @@
 ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
 ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
+; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
 ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
 ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 1c0b2a59d0693f..078a58f0139075 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -327,6 +327,9 @@
 .attribute arch, "rv32i_smepmp1p0"
 # CHECK: attribute      5, "rv32i2p1_smepmp1p0"
 
+.attribute arch, "rv32i_smrnmi1p0"
+# CHECK: attribute      5, "rv32i2p1_smrnmid1p0"
+
 .attribute arch, "rv32i_ssccfg1p0"
 # CHECK: attribute      5, "rv32i2p1_ssccfg1p0"
 
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index ae1af1fc8abc35..1e13d5c60b8a48 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
 csrrs t2, 0xB1F, zero
 
 
+######################################
+# Machine Counter Setup
+######################################
+# mnscratch
+# name
+# CHECK-INST: csrrs t1, mnscratch, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74]
+# CHECK-INST-ALIAS: csrr t1, mnscratch
+# uimm12
+# CHECK-INST: csrrs t2, mnscratch, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74]
+# CHECK-INST-ALIAS: csrr t2, mnscratch
+# name
+csrrs t1, mnscratch, zero
+# uimm12
+csrrs t2, 0x740, zero
+
+# mnepc
+# name
+# CHECK-INST: csrrs t1, mnepc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74]
+# CHECK-INST-ALIAS: csrr t1, mnepc
+# uimm12
+# CHECK-INST: csrrs t2, mnepc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74]
+# CHECK-INST-ALIAS: csrr t2, mnepc
+# name
+csrrs t1, mnepc, zero
+# uimm12
+csrrs t2, 0x741, zero
+
+# mncause
+# name
+# CHECK-INST: csrrs t1, mncause, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74]
+# CHECK-INST-ALIAS: csrr t1, mncause
+# uimm12
+# CHECK-INST: csrrs t2, mncause, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74]
+# CHECK-INST-ALIAS: csrr t2, mncause
+# name
+csrrs t1, mncause, zero
+# uimm12
+csrrs t2, 0x742, zero
+
+# mnstatus
+# name
+# CHECK-INST: csrrs t1, mnstatus, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74]
+# CHECK-INST-ALIAS: csrr t1, mnstatus
+# uimm12
+# CHECK-INST: csrrs t2, mnstatus, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74]
+# CHECK-INST-ALIAS: csrr t2, mnstatus
+# name
+csrrs t1, mnstatus, zero
+# uimm12
+csrrs t2, 0x744, zero
+
+
 ######################################
 # Machine Counter Setup
 ######################################
diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s
index d0446dbd1f8656..e9ed3c3d0d0ab7 100644
--- a/llvm/test/MC/RISCV/priv-invalid.s
+++ b/llvm/test/MC/RISCV/priv-invalid.s
@@ -2,6 +2,8 @@
 
 mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
 
+mnret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+
 sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
 
 sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s
index 561c76bf4fa295..75dc8c6b98cc52 100644
--- a/llvm/test/MC/RISCV/priv-valid.s
+++ b/llvm/test/MC/RISCV/priv-valid.s
@@ -17,6 +17,10 @@ sret
 # CHECK: encoding: [0x73,0x00,0x20,0x30]
 mret
 
+# CHECK-INST: mnret
+# CHECK: encoding: [0x73,0x00,0x20,0x70]
+mnret
+
 # CHECK-INST: wfi
 # CHECK: encoding: [0x73,0x00,0x50,0x10]
 wfi
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 33944b64dc1577..ded43a4ff7875a 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1065,6 +1065,7 @@ R"(All available -march extensions for RISC-V
     smcdeleg             1.0
     smcsrind             1.0
     smepmp               1.0
+    smrnmi               1.0
     smstateen            1.0
     ssaia                1.0
     ssccfg               1.0

github-actions · 2024-10-09T16:55:22Z

⚠️ We detected that you are using a GitHub private e-mail address to contribute to the repo.
Please turn off Keep my email addresses private setting in your account.
See LLVM Discourse for more information.

asb · 2024-10-09T16:59:09Z

Welcome to the project @dong-miao! I'm not sure why the auto-labeler didn't kick in to attach the backend:RISC-V label (this is used to help ping the right people), but I've added that now.

Just two quick comments as it's end of day here so I can't review properly right now:

We try to make the PR title and description match the intended commit. For a something like this, we'd typically name it something like "[RISCV][MC] Add support for the Smrnmi extension"
Please add a release note to the RISC-V section in llvm/docs/ReleaseNotes.md. e.g. "Support was added for the Smrnmi extension."

wangpc-pp · 2024-10-10T03:32:05Z

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
                             [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
                             [SDNPHasChain, SDNPOptInGlue]>;
+def riscv_mnret_glue : SDNode<"RISCVISD::MNRET_GLUE", SDTNone,


This should be in another patch for CodeGen. And, do we really need it? It will only be used in supervisor IIUC.

RISCVISD::MNRET_GLUE isn't defined in this patch so it should definitely be removed.

Thanks, I have removed the relevant content.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

topperc · 2024-10-10T03:55:15Z

llvm/test/MC/RISCV/machine-csr-names.s

@@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
 csrrs t2, 0xB1F, zero


+######################################
+# Machine Counter Setup


Section title is incorrect.

The registers are already tested in rv32-machine-csr-names.s but they should be in this file. That was a mistake.

Okay, I haven't made any modifications to the content of this file

llvm/lib/Target/RISCV/RISCVInstrInfo.td

topperc · 2024-10-10T16:50:48Z

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -931,6 +931,10 @@ def FeatureStdExtSmepmp
    : RISCVExtension<"smepmp", 1, 0,
                     "'Smepmp' (Enhanced Physical Memory Protection)">;

+def FeatureStdExtSmrnmi
+    : RISCVExtension<"smrnmi", 1, 0,
+                     "'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">;


I don't think we usually write "Extension for" in the description.

Okay, I have deleted the relevant content.

lenary · 2024-10-21T14:21:37Z

llvm/docs/RISCVUsage.rst

@@ -129,6 +129,7 @@ on support follow.
     ``Smcdeleg``      Supported
     ``Smcsrind``      Supported
     ``Smepmp``        Supported
+     ``Smrnmi``        Supported


This should probably be "Assembly Support" - some of the other *ret instructions have support in clang for __attribute((interrupt(<kind>))) which doesn't yet exist for mnret - there's no obligation to add this support in the first PR, but this should mean no one expects it has the same level of featureas as the other *ret instructions.

Suggested change

``Smrnmi`` Supported

``Smrnmi`` Assembly Support

Okay, thanks for your help.

Co-authored-by: Sam Elliott <sam@lenary.co.uk>

lenary

LGTM.

Xinlong-Wu · 2024-10-25T07:41:27Z

@dong-miao don‘t have write access, I help him to merge

github-actions · 2024-10-25T07:41:42Z

@dong-miao Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues.

How to do this, and the rest of the post-merge process, is covered in detail here.

If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again.

If you don't get any reports, no action is required from you. Your changes are working as expected, well done!

This commit has completed the Extension for Resumable Non Maskable Interrupts, adding four CRSs and one Trap-Return instruction. Specification link:["Smrnmi" Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc) --------- Co-authored-by: Sam Elliott <sam@lenary.co.uk>

dong-miao added 14 commits October 9, 2024 18:49

Update RISCVSystemOperands.td

c7a9b55

Update machine-csr-names.s

91125a1

Update riscv-target-features.c

6014139

Update RISCVUsage.rst

8706286

Update RISCVFeatures.td

6844754

Update attributes.ll

7922fbb

Update attributes.ll

c8fccb5

Update attribute-arch.s

3d6f0fe

Update RISCVISAInfoTest.cpp

805fd8a

Update riscv-target-features.c

35588a3

Update riscv-target-features.c

f497950

Update RISCVInstrInfo.td

7db01e7

Update priv-valid.s

29eaa52

Update priv-invalid.s

3c5f6d1

tschuett requested a review from asb October 9, 2024 13:03

asb added the backend:RISC-V label Oct 9, 2024

dtcxzyw requested review from topperc and wangpc-pp October 9, 2024 16:58

wangpc-pp reviewed Oct 10, 2024

View reviewed changes

topperc changed the title ~~Add Smrnmi extension~~ [RISCV] Add Smrnmi extension Oct 10, 2024

topperc reviewed Oct 10, 2024

View reviewed changes

lenary reviewed Oct 10, 2024

View reviewed changes

llvm/lib/Target/RISCV/RISCVInstrInfo.td Show resolved Hide resolved

topperc reviewed Oct 10, 2024

View reviewed changes

dong-miao added 3 commits October 21, 2024 16:44

Update RISCVFeatures.td

1858bed

Update RISCVFeatures.td

dedaf01

Update RISCVInstrInfo.td

3086afc

dong-miao added 5 commits October 21, 2024 16:52

Update RISCVSystemOperands.td

95567b3

Update priv-invalid.s

88dfe2b

Update priv-valid.s

1350674

Create smrnmi-invalid.s

116aa08

Create smrnmi-valid.s

e077536

lenary reviewed Oct 21, 2024

View reviewed changes

dong-miao and others added 4 commits October 22, 2024 16:07

Update llvm/docs/RISCVUsage.rst

6249ffb

Co-authored-by: Sam Elliott <sam@lenary.co.uk>

Merge branch 'main' into develop

2452b33

Update attribute-arch.s

5a58844

Update print-supported-extensions-riscv.c

769d395

lenary approved these changes Oct 24, 2024

View reviewed changes

Xinlong-Wu merged commit ed6ddff into llvm:main Oct 25, 2024
9 checks passed

dong-miao deleted the develop branch October 25, 2024 08:05

frobtech mentioned this pull request Oct 25, 2024

p/libc fexcept t #113664

Closed

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

[RISCV] Add Smrnmi extension #111668

[RISCV] Add Smrnmi extension #111668

dong-miao commented Oct 9, 2024

github-actions bot commented Oct 9, 2024

llvmbot commented Oct 9, 2024

github-actions bot commented Oct 9, 2024

asb commented Oct 9, 2024

wangpc-pp Oct 10, 2024 •

edited

Loading

topperc Oct 10, 2024

dong-miao Oct 21, 2024

topperc Oct 10, 2024

dong-miao Oct 21, 2024

topperc Oct 10, 2024

dong-miao Oct 21, 2024

lenary Oct 21, 2024

dong-miao Oct 22, 2024

lenary left a comment

Xinlong-Wu commented Oct 25, 2024

github-actions bot commented Oct 25, 2024

[RISCV] Add Smrnmi extension #111668

[RISCV] Add Smrnmi extension #111668

Conversation

dong-miao commented Oct 9, 2024

github-actions bot commented Oct 9, 2024

llvmbot commented Oct 9, 2024

github-actions bot commented Oct 9, 2024

asb commented Oct 9, 2024

wangpc-pp Oct 10, 2024 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

lenary left a comment

Choose a reason for hiding this comment

Xinlong-Wu commented Oct 25, 2024

github-actions bot commented Oct 25, 2024

wangpc-pp Oct 10, 2024 •

edited

Loading